High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Clock-Delayed Domino for Adder and Combinational Logic Desig
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects
International Journal of Circuit Theory and Applications
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Dynamic logic families have been shown to offer performance advantages over traditional CMOS logic. Their operation is based on the use of a clock signal that provides two operation phases: the precharge phase and evaluation phase. The precharge phase is setting the circuit at a predefined initial state while the actual logic response is determined during the evaluation phase. In this paper we examine potential advantages when an additional phase, called pre-evaluation, is introduced. During this phase a restricted voltage swing occurs depending on the desired outcome. This voltage swing is amplified during the final evaluation in order to produce the final logic response. By restricting the required voltage swing at internal logic nodes (especially in case of those presenting high capacitance) we are able to achieve higher performance coupled with reduced power consumption.