Skewed CMOS: noise-tolerant high-performance low-power static circuit family

Authors:
Alexandre Solomatnikov;Dinesh Somasekhar;Naran Sirisantana;Kaushik Roy
Affiliations:
Department of Electrical Engineering, Stanford University, Stanford, CA;Circuits Research Laboratory, Intel Corporation, Portland, OR;Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

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Abstract

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and they are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate applicability of proposed logic style 0.35 µm 5.56 ns CMOS 16 × 16 bit multiplier has been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed power of 195 mW due to low clock load.