Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
Branching programs and binary decision diagrams: theory and applications
Branching programs and binary decision diagrams: theory and applications
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Towards One-Pass Synthesis
IEEE Transactions on Computers
Equational binary decision diagrams
LPAR'00 Proceedings of the 7th international conference on Logic for programming and automated reasoning
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
An Efficient Gate Library for Ambipolar CNTFET Logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards structured ASICs using polarity-tunable Si nanowire transistors
Proceedings of the 50th Annual Design Automation Conference
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We present a novel class of decision diagrams, called Biconditional Binary Decision Diagrams (BBDDs), that enable efficient logic synthesis for XOR-rich circuits. BBDDs are binary decision diagrams where the Shannon's expansion is replaced by the biconditional expansion. Since the biconditional expansion is based on the XOR/XNOR operations, XOR-rich logic circuits are efficiently represented and manipulated with canonical Reduced and Ordered BBDDs (ROBBDDs). Experimental results show that ROBBDDs have 37% fewer nodes on average compared to traditional ROBDDs. To exploit this opportunity in logic synthesis for XOR-rich circuits, we developed a BBDD-based One-Pass Synthesis (OPS) methodology. The BBDD-based OPS is capable to harness the potential of novel XOR-efficient devices, such as ambipolar transistors. Experimental results show that our logic synthesis methodology reduces the number of ambipolar transistors by 49.7% on average with respect to state-of-art commercial logic synthesis tool. Considering CMOS technology, the BBBD-based OPS reduces the device count by 31.5% on average compared to commercial synthesis tool.