Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Constructive library-aware synthesis using symmetries
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Resynthesis of multi-level circuits under tight constraints using symbolic optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A new enhanced constructive decomposition and mapping algorithm
Proceedings of the 40th annual Design Automation Conference
Disjunctive Decomposition of Switching Functions Using Symmetry Information
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Constructive multi-level synthesis by way of functional properties
Constructive multi-level synthesis by way of functional properties
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Detecting support-reducing bound sets is an important step in Boolean decomposition. It affects both the quality and the runtime of several applications in technology mapping and re-synthesis. This paper presents an efficient heuristic method for detecting support-reducing bound sets using two-cofactor symmetries. Experiments on the MCNC and ITC benchmarks show an average 40x speedup over the published exhaustive method for bound set construction.