Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Low power ATPG for path delay faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact path delay fault coverage with fundamental ZBDD operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A recent work describes an ATPG for path delay faults that limits the power dissipated by the test patterns to a given bound. However, the power dissipated by the intermediate patterns while applying the test patterns in a sequence is not considered. Experiments with test patterns derived from different ATPGs has shown that the switching activity due to intermediate patterns dissipate considerable power. This paper proposes a method to incorporate stability functions in a functional ATPG to derive test vectors that guarantee reduced power dissipation by the intermediate patterns without loss in PDF coverage.