Introduction to algorithms
Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Optimum retiming of large sequential circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Retiming with logic duplication transformation: theory and an application to partial scan
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
Exploiting Retiming in a Guided Simulation Based Validation Methodology
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Retiming with logic duplication transformation: theory and an application to partial scan
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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This paper presents software (model) transformations that can be used to effectively generate high fault coverage test sets. Unlike synthesis or design for testability methods which involve hardware modifications, this approach does not modify the hardware design. Instead, it transforms a software model of the design into a new software model that has desirable testability properties. A sequential test generator generates tests for the new model. The new model may not be functionally equivalent to the original design but our transformations guarantee that the tests generated for the new model can always be inverse mapped to serve as tests for the original design. Experimental results show that significantly high fault coverage can be achieved by using this approach.