Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Resynthesis and retiming for optimum partial scan
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan with pre-selected scan signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
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A Abstract: Retiming when performed in conjunction with logic duplication results in many different circuit configurations that are not obtainable by retiming alone. These circuit configurations (we call RLD configurations) have significantly different area, performance and testability characteristics. We develop a formal framework that allows consideration of all configurations that can be designed using the RLD transformation. The RLD configurations are represented as a feasible solution set of an integer linear program (ILP). The objective function of the ILP can be used to explore the trade off between different design and testability metrics. We Identify an approach to solve several useful special cases of the ILP in polynomial time. As far as we know, our framework is the first to treat RLD transformations in a formal way. To demonstrate the effectiveness of our framework, we consider the application of RLD transformation to partial scan. A recent technique determines the desired positions for scan flip-flops and then employs an RLD transformation to achieve this repositioning. No attempt is made to reduce the area overhead due to logic duplication. Using our RLD framework, we develop an efficient polynomial time algorithm to compute the desired RLD configuration for which the number of logic nodes duplicated is also minimized. Experimental results on large ISCAS 89 benchmark circuits are included to show that our algorithm is indeed very efficient.