The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
On improving fault diagnosis for synchronous sequential circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Advanced Fault Collapsing (Logic Circuits Testing)
IEEE Design & Test
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Diagnosis oriented test pattern generation
EURO-DAC '90 Proceedings of the conference on European design automation
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Diagnosis and Fault Equivalence in Combinational Circuits
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
Identification of Equivalent Faults in Logic Networks
IEEE Transactions on Computers
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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Effective diagnosis of integrated circuits relies critically on the quality of diagnostic test vectors. Diagnostic test pattern generation aims at producing test vectors that distinguish between all distinguishable pairs of faults, and proving the remaining pairs of faults to be indistinguishable. Proving indistinguishabilities, much like proving undetectabilities in the case of detection-oriented test pattern generation, requires substantial computational effort. In this paper, we simplify the problem by showing that a significant number of indistinguishability relations can be proven implicitly, with little computational effort. Sequential indistinguishability is characterized and conditions for the identification of new indistinguishability relations based on already existing relations are established. Experiments on the ISCAS 89 benchmark circuits are presented to indicate the significant improvements achievable by the implicit identification of indistinguishabilities.