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SIGMOD '93 Proceedings of the 1993 ACM SIGMOD international conference on Management of data
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Symbolic model checking using SAT procedures instead of BDDs
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Multi-node static logic implications for redundancy identification
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
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ATS '97 Proceedings of the 6th Asian Test Symposium
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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Proceedings of the conference on Design, automation and test in Europe
Local Search for Boolean Relations on the Basis of Unit Propagation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Enhanced 3-Valued Logic/Fault Simulation for Full Scan Circuits using Implicit Logic Values
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel framework for logic verification in a synthesis environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic optimization and equivalence checking by implication analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation-directed invariant mining for software verification
Proceedings of the conference on Design, automation and test in Europe
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In this paper, we propose a novel technique on mining relationships in a sequential circuit to discover global constraints. In contrast to the traditional learning methods, our mining algorithm can find important relationships among several nodes efficiently. The nodes involved may often span several time-frames, thus improving the deductibility of the problem instance. Experimental results demonstrate that the application of these global constraints to SAT-based bounded sequential equivalence checking can achieve one to two orders of magnitude speedup. In addition, because it is orthogonal to the underlying SAT solver, it can help to enhance the efficacy of typical SAT based verification flows.