Enhanced 3-Valued Logic/Fault Simulation for Full Scan Circuits using Implicit Logic Values

Authors:
Seiji Kajihara;Kewal K. Saluja;Sudhakar M. Reddy
Affiliations:
Kyushu Institute of Technology, Japan;University of Wisconsin-Madison;University of Iowa, Iowa City
Venue:
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Year:
2004

Citing 0
Cited 2

Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Mining global constraints for improving bounded sequential equivalence checking

Proceedings of the 43rd annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain.This increase has also pushed the need for higher data-transfer rates between ...