Partitioning logic circuits to maximize fault resolution

Authors:
Ayee Goundan;John P. Hayes
Affiliations:
-;-
Venue:
DAC '76 Proceedings of the 13th Design Automation Conference
Year:
1976

Citing 0
Cited 3

LORES - Logic Reorganization System

DAC '78 Proceedings of the 15th Design Automation Conference
Design of Totally Fault Locatable Combinational Networks

IEEE Transactions on Computers
Identification of Equivalent Faults in Logic Networks

IEEE Transactions on Computers

Quantified Score

Hi-index	0.01

Visualization

Abstract

Two techniques are discussed for partitioning logic circuits to maximize the resolution of stuck-line faults. One technique exploits the inherent fault resolution of the circuit by attempting to force equivalent faults into the same module. The other involves inserting control points to separate members of equivalent fault classes, a technique called fault class splitting. Some new methods for identifying equivalent faults are also presented.