LORES - Logic Reorganization System

Authors:
Shunichiro Nakamura;Shinichi Murai;Chiyoji Tanaka;Masayuki Terai;Hideo Fujiwara;Kozo Kinoshita
Affiliations:
-;-;-;-;-;-
Venue:
DAC '78 Proceedings of the 15th Design Automation Conference
Year:
1978

Citing 2
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Abstract

Described is the outline and the experimental results of the system which automatically restructures and partitions a logic circuit consisting of standard SSI's and MSI's so that the gate types and the numbers of input/output terminals of the reorganized circuits are within the restrictions of the specified LSI.