LORES - Logic Reorganization System
DAC '78 Proceedings of the 15th Design Automation Conference
Developments in verification of design correctness (A Tutorial)
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Engineering Data Management System (EDMS) for computer aided design of digital computers
DAC '74 Proceedings of the 11th Design Automation Workshop
A Testable Design of Logic Circuits Under Highly Observable Condition
IEEE Transactions on Computers - Special issue on fault-tolerant computing
An over-cell gate array channel router
DAC '83 Proceedings of the 20th Design Automation Conference
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The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. Automatic translation of logic circuit is done by macro expansion technique coupled with redundant logic reduction procedures.