Developments in verification of design correctness (A Tutorial)

  • Authors:
  • W. E. Cory;W. M. VanCleemput

  • Affiliations:
  • -;-

  • Venue:
  • DAC '80 Proceedings of the 17th Design Automation Conference
  • Year:
  • 1980

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Abstract

This paper reviews recent developments in the verification of digital systems designs. The emphasis is on proof of functional correctness. Some of the techniques reviewed are symbolic simulation (including parallel simulation of HDL descriptions), dataflow verification by grammar construction, comparison of manually generated design with automated design, and functional abstraction.