Reliability modeling techniques for self-repairing computer systems
ACM '69 Proceedings of the 1969 24th national conference
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
Reliability Modeling for Fault-Tolerant Computers
IEEE Transactions on Computers
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
14.2 Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A New Approach to the Evaluation of the Reliability of Digital Systems
IEEE Transactions on Computers
Fault-Tolerant Computing: An Introduction and a Perspective
IEEE Transactions on Computers
A Reliability Model for Various Switch Designs in Hybrid Redundancy
IEEE Transactions on Computers
Optimal system size for k-out-of-n systems with competing failure modes
Mathematical and Computer Modelling: An International Journal
| Hi-index | 14.99 |
The classical reliability model for N-modular redundancy (NMR) assumes the network to be failed when a majority of modules which drive the same voter fail. It has long been known that this model is pessimistic since there are instances, termed compensating module failures, where a majority of the modules fail but the network is nonfailed. A different module reliability model based on lead reliability is proposed which has the classical NMR reliability model as a special case. Recent results from the area of test generation are employed to simplify the module reliability calculation under the lead reliability model. First a fault equivalent technique, based on functional equivalence of faults, is developed to determine the effect of compensating module failures on system reliability. This technique can increase the predicted mission time (the time the system is to operate at or above a given reliability) by at least 40 percent over the classical model prediction for simple networks. Since the fault equivalent technique is too complex for modeling of large circuits a second, computational simpler technique, based on fault dominance, is derived. It is then shown to yield results comparable to the fault equivalent technique. A more complex example circuit analyzed by the fault dominance model shows at least a 75 percent improvement in mission time due to modeling compensating module failures. A commercialy available 31 gate integrated circuit chip is also modeled to demonstrate the applicability of the technique to large circuits.