Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Fault-Tolerance of the Iterative Cell Array Switch for Hybrid Redundancy
IEEE Transactions on Computers
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
On Reliability Modeling and Analysis of Ultrareliable Fault-Tolerant Digital Systems
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
Reliability Modeling for Fault-Tolerant Computers
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Sequential Circuit Output Probabilities From Regular Expressions
IEEE Transactions on Computers
A New Approach to the Evaluation of the Reliability of Digital Systems
IEEE Transactions on Computers
Fault-Tolerant Computing: An Introduction and a Perspective
IEEE Transactions on Computers
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
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The paper discusses two methods to evaluate the signal reliability of the output of logical circuits. It is known that faults present in a circuit will not always cause the output of the circuit to be incorrect. Given the probability of faults occurring in the circuit and the probabilities of the input combinations, it is possible to determine the likelihood of the output being correct. The signal reliability of the output is thus defined as the probability that the circuit output is correct. The first method evaluates the contribution of each fault to the reliability of the circuit and requires the enumeration of the behavior of each fault in the entire fault set. The use of McCluskey and Clegg's characterization of faulty networks by evaluating the functional equivalence classes of the network is a way to reduce the amount of computation involved. Lower bounds can be obtained by considering a restricted fault set, for example, the single fault set. The second method uses a probabilistic model of logical circuits and consists of straightforward operations which can easily be automated. The method also yields the signal reliability and has the capability of very easily specifying the individual fault probabilities of all the circuit lines independently.