Fault-Tolerance of the Iterative Cell Array Switch for Hybrid Redundancy

Authors:
R. C. Ogus
Affiliations:
Digital Systems Laboratory, Stanford University
Venue:
IEEE Transactions on Computers
Year:
1974

Citing 0
Cited 7

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A Probabilistic Approach of Designing More Reliable Logic Gates with Asymmetric Input Faults

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Modular redundancy without voters decreases complexity of restoring organ

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A Reliability Model for Various Switch Designs in Hybrid Redundancy

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Abstract

The technique of hybrid redundancy has been used to protect those portions of a digital system which have to be made ultrareliable. Siewiorek and McCluskey have presented a new switch design for hybrid redundancy which is shown to be of less complexity than other switch designs presented in the literature.