Reliability modeling techniques for self-repairing computer systems
ACM '69 Proceedings of the 1969 24th national conference
An Iterative Cell Switch Design for Hybrid Redundancy
IEEE Transactions on Computers
A Highly Efficient Redundancy Scheme: Self-Purging Redundancy
IEEE Transactions on Computers
Fault-Tolerance of the Iterative Cell Array Switch for Hybrid Redundancy
IEEE Transactions on Computers
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
A framework for hardware-software tradeoffs in the design of fault-tolerant computers
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults
IEEE Transactions on Computers
IDAS: an integrated design automation system
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
Designs for dlagnosablllty and reliability in VLSI systems
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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This paper deals with a method for designing a digital system which will remain operational in spite of the failure of some of its components. A scheme and its realization are presented for automatically reconfiguring a 5MR (five modular redundancy system or 5-input majority voting system) into a triple modular redundancy (TMR) system under a single or double module failures. The scheme can tolerate a double fault followed by a single fault which can neither be tolerated by a 5MR nor by a hybrid redundancy system with a TMR core. It uses no spare units and the circuit realization is relatively simple. The modular structure of the logic design for the proposed scheme should make the testing of the system easier. The scheme can be used in both binary and multivalued systems.