Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Design for Testability A Survey
IEEE Transactions on Computers
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures
IEEE Transactions on Computers
A Highly Efficient Redundancy Scheme: Self-Purging Redundancy
IEEE Transactions on Computers
Model for transient and permanent error-detection and fault-isolation coverage
IBM Journal of Research and Development
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New concepts of Designs for Diagnosability and reliability are defined and developed in this paper. A diagnosable design of VLSI system is presented, in which fault isolation is realized by minimal additional hardware instead of traditional software diagnostic procedures such that the computation space and time for fault isolation are saved. Our fault-tolerant design uses on-line fault detection and isolation techniques, yields higher reliability with minimized hardware overhead of no more than 125% as opposed to over 200% in classical redundancy fault-tolerant designs. Furthermore, using our scheme, the ability to isolate intermittent faults is a significant improvement over the existing fault isolation methods because faults could be isolated right after they are detected.