Functional testing techniques for digital LSI/VLSI systems
DAC '84 Proceedings of the 21st Design Automation Conference
Testing functional faults in VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
The MIMOLA design system a computer aided digital processor design method
DAC '79 Proceedings of the 16th Design Automation Conference
Computer-aided logic synthesis based on a new multi-level hardware design language---lalsd ii
Computer-aided logic synthesis based on a new multi-level hardware design language---lalsd ii
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures
IEEE Transactions on Computers
The CMU RT-CAD system: an innovative approach to computer aided design
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
| Hi-index | 0.00 |
Computer-aided design tools are vital to the design of VLSI (very-large-scale integration). This paper presents a new integrated design automation system for describing, documenting, simulating, and synthesizing digital systems. The system consists of a new hardware description language, LALSD II; a translator; a simulator; and a logic synthesizer. The language allows the designer to describe a digital system at various levels of detail, to define modules for implementation, and to describe the system at the behavior level, the structure level, or both. The language can accurately describe the timing for various operations. It can precisely describe multilevel, parallel operations. LALSD II can describe synchronous, asynchronous, or mixed systems. The translator converts the language into a database for simulation and logic synthesis. It can translate each module of the system independently. This means that a designer can modify any module without retranslating other modules. The multilevel hierarchical simulator is a six-valued, table-driven, significant event simulator with selective trace capabilities. Synchronous, asynchronous, or mixed systems and concurrent events can also be simulated. It can simulate intricate timing relations among different components. The logic synthesizer accepts the database, the library of logic modules, the key modules, and the clock period specified by the user and produces the logic design in terms of logic modules and their interconnections.