Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
On the Design of Multiple Fault Diagnosable Networks
IEEE Transactions on Computers
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
IEEE Transactions on Computers
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests
IEEE Transactions on Computers
A Way to Find a Lower Bound for the Minimal Solution of the Covering Problem
IEEE Transactions on Computers
Circuit Structure and Switching Function Verification
IEEE Transactions on Computers
Minimization over Boolean graphs
IBM Journal of Research and Development
Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
Circuit Structure and Switching Function Verification
IEEE Transactions on Computers
| Hi-index | 14.99 |
A new approach is developed for finding multiple fault detection tests under quite arbitrary fault models. Computational results are reported and discussed.