Journal of the ACM (JACM)
Optimum Functional Decomposition for LUT-Based FPGA Synthesis
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Quasi-algebraic decompositions of switching functions
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
LUT-based FPGA Technology Mapping using Permissible Functions
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Minimization of Exclusive or and Logical Equivalence Switching Circuits
IEEE Transactions on Computers
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
IEEE Transactions on Computers
A Unified Theory of the Algebraic Topological Methods for the Synthesis of Switching Systems
IEEE Transactions on Computers
A Method for Generating Prime Implicants of a Boolean Expression
IEEE Transactions on Computers
The Characterization and Properties of Cascade Realizable Switching Functions
IEEE Transactions on Computers
Partitioning of Separating Edges: A New Approach to Combinational Logic Design
IEEE Transactions on Computers
Synthesis of Combinational Logic Using Decomposition and Probability
IEEE Transactions on Computers
A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods
IEEE Transactions on Computers
Circuit Structure and Switching Function Verification
IEEE Transactions on Computers
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
A relational approach to functional decomposition of logic circuits
ACM Transactions on Database Systems (TODS)
Computing support-minimal subfunctions during functional decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a systematic procedure for thed esign of gate-type combinational switching circuits without diredted loops. Each such circuit (Boolean graph) is in correspondence with a sequence of decompositions of the Boolean function which it realizes. A general approach to functional decomposition i s given and, in terms oaf convenient positional representation, efficient tests for the detection of decompositions are derived. These results are employed in the development of an alphabetic search procedure for determining minimum-cost Boolean graphs which satisfy any given design specifications.