Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automated Synthesis of Assertion Monitors using Visual Specifications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automatic generalized phase abstraction for formal verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Synthesizing SVA local variables for formal verification
Proceedings of the 44th annual Design Automation Conference
Efficient BMC for Multi-Clock Systems with Clocked Specifications
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
This paper presents a compilation procedure for synthesizing multiclock SVA properties for formal verification. The synthesis framework is built upon an existing compilation algorithm for single-clock SVA properties. While we could use the SVA rewriting rules to transform a multi-clock property into a single-clocked property and then apply existing techniques, instead we propose techniques to selectively model the multi-clock operators to produce a smaller checker logic. Through recursive construction and syntactic transformation, we are able demonstrate the efficiency of the technique and the generated checker logic is provably equivalent to the rewritten version.