A superimposition control construct for distributed systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
The B-book: assigning programs to meanings
The B-book: assigning programs to meanings
Stepwise Refinement of Action Systems
Proceedings of the International Conference on Mathematics of Program Construction, 375th Anniversary of the Groningen University
LICS '03 Proceedings of the 18th Annual IEEE Symposium on Logic in Computer Science
A Scalable Communication-Centric SoC Interconnect Architecture
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Formal methods and models for system design: a system level perspective
Formal methods and models for system design: a system level perspective
Formal development of NoC systems in B
Nordic Journal of Computing - Selected papers of the 17th nordic workshop on programming theory (NWPT'05), October 19-21, 2005
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks
AMS '07 Proceedings of the First Asia International Conference on Modelling & Simulation
Fault Tolerant Source Routing for Network-on-chip
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Refinement, Decomposition, and Instantiation of Discrete Models: Application to Event-B
Fundamenta Informaticae - This is a SPECIAL ISSUE ON ASM'05
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
Application Specific Routing Algorithms for Networks on Chip
IEEE Transactions on Parallel and Distributed Systems
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
A Condition of Deadlock-Free Routing in Mesh Network
ICINIS '09 Proceedings of the 2009 Second International Conference on Intelligent Networks and Intelligent Systems
Balanced Dimension-Order Routing for k-ary n-cubes
ICPPW '09 Proceedings of the 2009 International Conference on Parallel Processing Workshops
A system development process with Event-B and the Rodin platform
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs
PDP '10 Proceedings of the 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing
Modeling in Event-B: System and Software Engineering
Modeling in Event-B: System and Software Engineering
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
Proceedings of the Conference on Design, Automation and Test in Europe
Refinement and reachability in event_b
ZB'05 Proceedings of the 4th international conference on Formal Specification and Development in Z and B
Refinement-Preserving translation from event-b to register-voice interactive systems
IFM'12 Proceedings of the 9th international conference on Integrated Formal Methods
Formal development of wireless sensor-actor networks
Science of Computer Programming
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Three-dimensional Networks-on-Chip (3D NoC) have recently emerged essentially via the stacking of multiple layers of two-dimensional NoCs. The resulting structures can support a very high level of parallelism for both communication and computation as well as higher speeds, at the cost of increased complexity. To address the potential problems due to the highly complex NoCs, we study them with formal methods. In particular, we base our study on the refinement relation between models of the same system. We propose three abstract models of 3D NoCs, M0, M1, and M2 so that M0 ⊑ M1 ⊑ M2, where ''' denotes the refinement relation. Each of these models provides templates for communication constraints and guarantees the communication correctness. We then show how to employ one of these models for reasoning about the communication correctness of the XYZ-routing algorithm.