OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Refinement-Based modeling of 3d nocs
FSEN'11 Proceedings of the 4th IPM international conference on Fundamentals of Software Engineering
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip
Microprocessors & Microsystems
Junction based routing: a scalable technique to support source routing in large NoC platforms
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Reliable and adaptive network-on-chip architectures for cyber physical systems
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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This paper presents a new routing protocol of network-on-chip(Noc) called "Source Routing for Noc" (SRN) for fault tolerant communication of Systems-on-chip(Soc). The proposed SRN algorithm is composed of two mechanisms of Route Discovery and Route maintenance to allow nodes to discover and maintain source routes to arbitrary destinations in Noc, and all aspects of the protocol operate entirely on-demand allowing the routing packet overhead to scale automatically based on its need. The SNR algorithm in this paper demonstrates up to 50 % more fault tolerance comparing with the conventional algorithms. This new method can be easily adapted and implemented with lower cost due to less hardware overhead in SoC that integrate a large number of communicating IP cores.