An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip

  • Authors:
  • Farshad Safaei;Majed Valadbeigi

  • Affiliations:
  • Faculty of ECE, Shahid Beheshti University GC, Evin 1983963113, Tehran, Iran;Faculty of ECE, Shahid Beheshti University GC, Evin 1983963113, Tehran, Iran

  • Venue:
  • Microprocessors & Microsystems
  • Year:
  • 2012

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Abstract

The move towards nanoscale Integrated Circuits (ICs) increases performance and capacity, but poses process variation and reliability challenges which may cause several faults on routers in Networks-on-Chips (NoCs). While utilizing healthy routers in an NoC is desirable, faulty regions with different shapes are formed gathering faulty routers. Fault regions can be used to lead the fault-tolerant routing algorithms to perform data transmission between healthy routers. In this paper a distributed fault-tolerant routing methodology for mesh networks is proposed which supports static and dynamic fault model. The static fault model supports minimal routing path which tolerates both convex and concave fault regions, while keeping the area and power overhead at a minimum level. Moreover, unlike most previous methods that support dynamic fault models, the presented method is able to tolerate any number of faults with any shapes of fault regions without disabling healthy nodes. The performance of the method is extensively evaluated, and the results show that our proposed method is valid for mesh topology, which has graceful performance degradation and allows the network to remain fully operational facing with the failures.