An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip
Microprocessors & Microsystems
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The move towards nanoscale Integrated Circuits (ICs) increases performance and capacity, but poses process variation and reliability challenges which may cause several faults on routers in Networks-on-Chip (NoCs). While utilizing healthy routers in a NoC is desirable, faulty regions with different shapes are formed gathering faulty routers. Fault regions can be used to lead the fault-tolerant routing algorithms to perform data transmission between healthy routers. To prepare the underlying fault-tolerant routing algorithms to tolerate the fault regions, in this paper a new methodology is suggested to perform functional connection in a faulty 2-D mesh NoC with arbitrary fault patterns. This technique supports minimal routing path which tolerating both convex and concave fault regions, while keeping the area and power overhead at minimum level. Performance of the proposed methodology is simulated under different network conditions which show that it can provide graceful performance degradation in the presence of various fault patterns.