Investigation of transient fault effects in synchronous and asynchronous Network on Chip router
Journal of Systems Architecture: the EUROMICRO Journal
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip
Microprocessors & Microsystems
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Fault-tolerant design of Network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction -- these may be specific to architecture, interconnection, communication and application issues. Assessing the effectiveness of a particular fault-tolerant implementation can be a challenging task for designers, constrained with tight system performance specifications and other requirements In this paper, we provide a top-down view of fault-tolerance methods for NoC infrastructures, and present a range of metrics used for estimating their quality. We illustrate the use of these metrics by simulating a few simple but realistic fault-tolerant scenarios.