Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Model Checking
Practical Formal Verification in Microprocessor Design
IEEE Design & Test
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
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This document describes how the FORTE STE-based formal verification system was used to verify the RTL implementation of an error control code. The error control code considered is linear: its encoder and decoder proceed by matrix multiplication. Although that function is in essence combinational, its implementation in a high-performance microprocessor is done in a pipelined fashion. The additional state elements introduced by the pipelining quickly push an SMV-style model checker to its capacity limits. With the case-study presented in this document, we show that an STE-style model checker is better suited for this problem. We present two instances of the ECC verification problem. For the first we were able to combine an encoder and a decoder into one model for verification. For the second, such a combination was not possible and we resorted to verifying properties of a matrix that we extracted from the implementation.