Verifying SystemC using an intermediate verification language and symbolic simulation

Authors:
Hoang M. Le;Daniel Große;Vladimir Herdt;Rolf Drechsler
Affiliations:
University of Bremen, Bremen, Germany;Solvertec GmbH, Bremen, Germany;University of Bremen, Bremen, Germany;University of Bremen, Bremen, Germany and DFKI GmbH, Bremen, Germany
Venue:
Proceedings of the 50th Annual Design Automation Conference
Year:
2013

Citing 16
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Abstract

Formal verification of SystemC is challenging. Before dealing with symbolic inputs and the concurrency semantics, a front-end is required to translate the design to a formal model. The lack of such front-ends has hampered the development of efficient back-ends so far. In this paper, we propose an isolated approach by using an Intermediate Verification Language (IVL). This enables a SystemC-to-IVL translator (frond-end) and an IVL verifier (back-end) to be developed independently. We present a compact but general IVL that together with an extensive benchmark set will facilitate future research. Furthermore, we propose an efficient symbolic simulator integrating Partial Order Reduction. Experimental comparison with existing approaches has shown its potential.