The verification of cache coherence protocols
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
SIAM Journal on Computing
Lamport clocks: verifying a directory cache-coherence protocol
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Imagine: Media Processing with Streams
IEEE Micro
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Checking Cache-Coherence Protocols with TLA+
Formal Methods in System Design
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Using Lamport Clocks to Reason About Relaxed Memory Models
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Verifying Sequential Consistency on Shared-Memory Multiprocessors by Model Checking
IEEE Transactions on Parallel and Distributed Systems
Exploring, defining, and exploiting recent store value locality
Exploring, defining, and exploiting recent store value locality
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
Linking Simulation with Formal Verification at a Higher Level
IEEE Design & Test
Dynamic Verification of Sequential Consistency
Proceedings of the 32nd annual international symposium on Computer Architecture
The Complexity of Verifying Memory Coherence and Consistency
IEEE Transactions on Parallel and Distributed Systems
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Testing implementations of transactional memory
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
System Verilog for Verification
System Verilog for Verification
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
On-the-fly verification of memory consistency with concurrent relaxed scoreboards
Proceedings of the Conference on Design, Automation and Test in Europe
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Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to validate memory system implementation. Having a memory scoreboard, a high-level model of the memory, greatly aids simulation based validation, but accurate score-boards are complex to create since often they depend not only on the memory and consistency model but also on its specific implementation. This paper describes a methodology of using a relaxed scoreboard, which greatly reduces the complexity of creating these memory models. The relaxed scoreboard tracks the operations of the system to maintain a set of values that could possibly be valid for each memory location. By allowing multiple possible values, the model used in the scoreboard is only loosely coupled with the specific design, which decouples the construction of the checker from the implementation, allowing the checker to be used early in the design and to be built up incrementally, and greatly reduces the scoreboard design effort. We demonstrate the use of the relaxed scoreboard in verifying RTL implementations of two different memory models, Transactional Coherency and Consistency (TCC) and Relaxed Consistency, for up to 32 processors. The resulting checker has a performance slowdown of 19% for checking Relaxed Consistency, and less than 30% for TCC, allowing it to be used in all simulation runs.