Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Hole analysis for functional coverage data
Proceedings of the 39th annual Design Automation Conference
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Checking Cache-Coherence Protocols with TLA+
Formal Methods in System Design
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Runtime Refinement Checking of Concurrent Data Structures
Electronic Notes in Theoretical Computer Science (ENTCS)
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 0.00 |
Editor's note: This article uses simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. 驴Carl Pixley, Synopsys