ACM Transactions on Programming Languages and Systems (TOPLAS)
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Verification of a multiprocessor cache protocol using simulation relations and higher-order logic
Formal Methods in System Design - Special issue on computer-aided verification: special methods I
ACM Transactions on Programming Languages and Systems (TOPLAS)
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
SIAM Journal on Computing
Lamport clocks: verifying a directory cache-coherence protocol
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Multicast snooping: a new coherence method using a multicast address network
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Automatable verification of sequential consistency
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Expressing interesting properties of programs in propositional temporal logic
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic Verification of Parameterized Cache Coherence Protocols
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Using Formal Verification/Analysis Methods on the Critical Path in System Design: A Case Study
Proceedings of the 7th International Conference on Computer Aided Verification
Protocol Verification by Aggregation of Distributed Transactions
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Verification of the Futurebus+ Cache Coherence Protocol
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Model-checking of correctness conditions for concurrent objects
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Formal design and verification methods for shared memory systems
Formal design and verification methods for shared memory systems
Verification of distributed programs using representative interleaving sequences
Distributed Computing
Distributed Computing - Special issue: Verification of lazy caching
The Complexity of Verifying Memory Coherence and Consistency
IEEE Transactions on Parallel and Distributed Systems
Memory Model = Instruction Reordering + Store Atomicity
Proceedings of the 33rd annual international symposium on Computer Architecture
Store Atomicity for Transactional Memory
Electronic Notes in Theoretical Computer Science (ENTCS)
Model checking transactional memories
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Polymorphic Systems with Arrays, 2-Counter Machines and Multiset Rewriting
Electronic Notes in Theoretical Computer Science (ENTCS)
Verifying concurrent programs against sequential specifications
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
Security Verification of Hardware-enabled Attestation Protocols
MICROW '12 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops
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The memory model of a shared-memory multiprocessor is a contract between the designer and the programmer of the multiprocessor. A memory model is typically implemented by means of a cache-coherence protocol. The design of this protocol is one of the most complex aspects of multiprocessor design and is consequently quite error-prone. However, it is imperative to ensure that the cache-coherence protocol satisfies the shared-memory model. This paper presents a novel technique based on model checking to tackle this difficult problem for the important and well-known shared-memory model of sequential consistency. Surprisingly, verifying sequential consistency is undecidable in general, even for finite-state cache-coherence protocols. The key insight of this paper is that, in practice, cache-coherence protocols satisfy the properties of causality and data independence. Causality is the property that values of read events flow from values of write events. Data independence is the property that all traces can be generated by renaming data values from traces where the written values are pairwise distinct. We show that, if a causal and data independent system also has the property that the logical order of write events to each location is identical to their temporal order, then sequential consistency is decidable. We present a novel model checking algorithm to verify sequential consistency on such systems for a finite number of processors and memory locations and an arbitrary number of data values.