Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
Branching vs. Linear Time: Final Showdown
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
The common fragment of CTL and LTL
FOCS '00 Proceedings of the 41st Annual Symposium on Foundations of Computer Science
Combining System Level Modeling with Assertion Based Verification
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A topological characterization of weakness
Proceedings of the twenty-fourth annual ACM symposium on Principles of distributed computing
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Resets vs. aborts in linear temporal logic
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Wolf: bug hunter for concurrent software using formal methods
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
The theory and practice of SALT
NFM'11 Proceedings of the Third international conference on NASA Formal methods
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PSL is a property specification language recently standardized as IEEE 1850TM-2005 PSL. It includes as its temporal layer a linear temporal logic that enhances LTL with regular expressions and other useful features. PSL and its precursor, Sugar, have been used by the IBM Haifa Research Laboratory for formal verification of hardware since 1993, and for informal (dynamic, simulation runtime) verification of hardware since 1997. More recently both Sugar and PSL have been used for formal, dynamic, and runtime verification of software. In this paper I will introduce PSL and briefly touch on theoretical and practical issues in the use of PSL for dynamic and runtime verification.