Simulation-guided property checking based on a multi-valued AR-automata
Proceedings of the conference on Design, automation and test in Europe
Causality based generation of directed test cases
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Model Checking of Safety Properties
Formal Methods in System Design
Model Checking of Safety Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal Verification of an Industrial System-on-a-Chip
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis
Electronic Notes in Theoretical Computer Science (ENTCS)
Object-oriented modelling and specification using SHE
Computer Languages
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"Verification" of large multiprocessor designs currently heavily on simulation. Formal techniques such as model checking are typically only applied to small parts of the system, due to issues of computational and notational complexity. With these two facts in mind the authors have designed a platform which aims to help bridge the gap between formal verification and simulation. They present a temporal logic specification language which includes constructs for specifying system behavior at a high level of abstraction, and discuss its use in simulation and model checking.