The Art of Electronics
Formal Methods in System Design
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Large-scale application of formal verification: from fiction to fact
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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Arbiters are commonly used components in electronic systems to control access to shared resources. In this paper, we describe a novel method to check starvation in random priority-based arbiters. Typical implementations of random priority-based arbiters use pseudo-random number generators such as linear feedback shift registers (LFSRs) which makes them sequentially deep precluding a direct analysis of the design. The proposed technique checks a stronger bounded-starvation property; if the stronger property fails, we use the counter-example to construct an underapproximation abstraction. We next check the original property on the abstraction to check for its validity. We have found the approach to be a very effective bug hunting technique to reveal starvation issues in LFSR-based arbiters. We describe its successful application on formal verification of arbiters on a commercial processor design.