Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
A new partial order reduction algorithm for concurrent system verification
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
A partial order approach to branching time logic model checking
Information and Computation
Model checking
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
Another Look at LTL Model Checking
Formal Methods in System Design
Static Partial Order Reduction
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A General Approach to Partial Order Reductions in Symbolic Verification (Extended Abstract)
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
NUSMV: A New Symbolic Model Verifier
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
The Engineering of a Model Checker: The Gnu i-Protocol Case Study Revisited
Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking
Efficient Symbolic Model Checking for Process Algebras
Formal Methods for Industrial Critical Systems
Communicating Process Architectures 2009 - WoTUG-32, Volume 67 Concurrent Systems Engineering Series
Communicating Process Architectures 2009 - WoTUG-32, Volume 67 Concurrent Systems Engineering Series
| Hi-index | 0.00 |
BDD-based symbolic techniques and partial-order reduction (POR) are two fruitful approaches to deal with the combinatorial explosion of model checking. Unfortunately, past experience has shown that BDD-based techniques do not work well for loosely-synchronized models, whereas POR methods allow explicit-state model checkers to deal with large concurrent models. This paper presents an algorithm that combines symbolic model checking and POR to verify linear temporal logic properties without the next operator (LTLX), which performs better on models featuring asynchronous processes. Our algorithm adapts and combines three methods: Clarke et al.'s tableau-based symbolic LTL model checking, Iwashita et al.'s forward symbolic CTL model checking and Lerda et al.'s ImProviso symbolic reachability with POR. We present our approach, outline the proof of its correctness, and present a prototypal implementation and an evaluation on two examples.