An Efficient Partial Order Reduction Algorithm with an Alternative Proviso Implementation
Formal Methods in System Design
SPPV: a new formal verification environment
Journal of Computing Sciences in Colleges
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Combining partial-order reduction and symbolic model checking to verify LTL properties
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Supporting domain-specific state space reductions through local partial-order reduction
ASE '11 Proceedings of the 2011 26th IEEE/ACM International Conference on Automated Software Engineering
Towards distributed verification of petri nets properties
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
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