A new partial order reduction algorithm for concurrent system verification

  • Authors:
  • Ratan Nalumasu;Ganesh Gopalakrishnan

  • Affiliations:
  • Univ. of Utah, Salt Lake City;Univ. of Utah, Salt Lake City

  • Venue:
  • CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
  • Year:
  • 1997

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Abstract