Modeling concurrency with partial orders
International Journal of Parallel Programming
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
A new partial order reduction algorithm for concurrent system verification
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Symbolic Model Checking
| Hi-index | 0.00 |
The increasing complexity of hardware systems necessitates the development of new methods to test the correctness of their operation. Lately, Formal Verification has proven to be a powerful alternative to conventional simulation and testing methods. In this paper we present a formal verification software environment, SPPV, based on a formal verification technique referred to as Series-Parallel Poset Verification.