Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Design and validation of computer protocols
Design and validation of computer protocols
Reasoning about parallel architectures
Reasoning about parallel architectures
Formal specification of abstract memory models
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A stubborn attack on state explosion
Formal Methods in System Design - Special issue on computer-aided verification: special methods I
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
A new partial order reduction algorithm for concurrent system verification
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Stubborn set methods for process algebras
POMIV '96 Proceedings of the DIMACS workshop on Partial order methods in verification
Partial order reduction: linear and branching temporal logics and process algebras
POMIV '96 Proceedings of the DIMACS workshop on Partial order methods in verification
Verifying hardware in its software context
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Using “test model-checking” to verify the Runway-PA8000 memory model
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Reduction: a method of proving properties of parallel programs
Communications of the ACM
Handbook of Theoretical Computer Science: Formal Models and Semantics
Handbook of Theoretical Computer Science: Formal Models and Semantics
Coverage Preserving Reduction Strategies for Reachability Analysis
Proceedings of the IFIP TC6/WG6.1 Twelth International Symposium on Protocol Specification, Testing and Verification XII
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
PV: An Explicit Enumeration Model-Checker
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Formal modeling and validation applied to a commercial coherent bus: a case study
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Memory Efficient Algorithms for the Verification of Temporal Properties
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
All from One, One for All: on Model Checking Using Representatives
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
On-the-Fly Verification with Stubborn Sets
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract)
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Using Partial Orders for the Efficient Verification of Deadlock Freedom and Safety Properties
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
A partial order approach to branching time logic model checking
ISTCS '95 Proceedings of the 3rd Israel Symposium on the Theory of Computing Systems (ISTCS'95)
Formal design and verification methods for shared memory systems
Formal design and verification methods for shared memory systems
A Distributed Partial Order Reduction Algorithm
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
State Space Reduction by Proving Confluence
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Cluster-Based Partial-Order Reduction
Automated Software Engineering
Iterative context bounding for systematic testing of multithreaded programs
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Resource-Aware Verification Using Randomized Exploration of Large State Spaces
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Analysing scientific workflows with Computational Tree Logic
Cluster Computing
Partial Order Reductions Using Compositional Confluence Detection
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Some solutions to the ignoring problem
Proceedings of the 14th international SPIN conference on Model checking software
Partial-Order reduction for general state exploring algorithms
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
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This paper presents a partial order reduction algorithm called Twophase that generates a significantly reduced state space on a large class of practical protocols over alternative algorithms in its class. The reduced state-space generated by Twophase preserves all CTL*-X assertions. Twophase achieves this reduction by following an alternative implementation of the proviso step. In particular, Twophase avoids the in-stack check that other tools use in order to realize the proviso step. In this paper, we demonstrate that the in-stack check is inefficient in practice, and demonstrate a much simpler alternative method of realizing the proviso. Twophase can be easily combined with an on-the-fly model-checking algorithm to reduce memory requirements further. A simple but powerful selective caching scheme can also be easily added to Twophase.A version of Twophase using on-the-fly model-checking and selective caching has been implemented in a model-checker called PV (Protocol Verifier) and is in routine use on large problems. PV accepts a proper subset of Promela and a never automaton expressing the LTL-X assertion to be verified. PV has helped us complete full state-space search several orders of magnitude faster than all alternative tools available in its class on dozens of real protocols. PV has helped us detect bugs in real Distributed Shared Memory cache coherency protocols that were missed during incomplete search using alternate tools.