Design and validation of computer protocols
Design and validation of computer protocols
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Formal modeling and validation applied to a commercial coherent bus: a case study
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
An Efficient Partial Order Reduction Algorithm with an Alternative Proviso Implementation
Formal Methods in System Design
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PV (Protocol Verifier) is an explicit enumeration based modelchecker for verifying finite state systems for next-time free LTL (LTL-X) properties. It implements a new partial order reduction algorithm, called Two-phase, that works in conjunction with selective caching to combat the state explosion problem faced by model-checkers.