Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
SIGCOMM '87 Proceedings of the ACM workshop on Frontiers in computer communications technology
A tight upper bound on the cover time for random walks on graphs
Random Structures & Algorithms
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Model checking
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Directed explicit model checking with HSF-SPIN
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Model checking Java programs using structural heuristics
ISSTA '02 Proceedings of the 2002 ACM SIGSOFT international symposium on Software testing and analysis
An Efficient Partial Order Reduction Algorithm with an Alternative Proviso Implementation
Formal Methods in System Design
An analysis of bistate hashing
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Improved probabilistic verification by hash compaction
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
IF: A Validation Environment for Timed Asynchronous Systems
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
A Probabilistic Approach to Automatic Verification of Concurrent Systems
APSEC '01 Proceedings of the Eighth Asia-Pacific on Software Engineering Conference
Exploring very large state spaces using genetic algorithms
International Journal on Software Tools for Technology Transfer (STTT) - Special section on tools and algorithms for the construction and analysis of systems
Enhancing random walk state space exploration
Proceedings of the 10th international workshop on Formal methods for industrial critical systems
State space exploration using feedback constraint generation and Monte-Carlo sampling
Proceedings of the the 6th joint meeting of the European software engineering conference and the ACM SIGSOFT symposium on The foundations of software engineering
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Deep random search for efficient model checking of timed automata
Proceedings of the 13th Monterey conference on Composition of embedded systems: scientific and industrial issues
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Uniform Monte-Carlo model checking
FASE'11/ETAPS'11 Proceedings of the 14th international conference on Fundamental approaches to software engineering: part of the joint European conferences on theory and practice of software
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Exhaustive verification often suffers from the state-explosion problem, where the reachable state space is too large to fit in main memory. For this reason, and because of disk swapping, once the main memory is full very little progress is made, and the process is not scalable. To alleviate this, partial verification methods have been proposed, some based on randomized exploration, mostly in the form of random walks. In this paper, we enhance partial, randomized state-space exploration methods with the concept of resource-awareness: the exploration algorithm is made aware of the limits on resources, in particular memory and time. We present a memory-aware algorithm that by design never stores more states than those that fit in main memory. We also propose criteria to compare this algorithm with similar other algorithms. We study properties of such algorithms both theoretically on simple classes of state spaces and experimentally on some preliminary case studies.