Stubborn sets for reduced state generation
APN 90 Proceedings on Advances in Petri nets 1990
A partial approach to model checking
Papers presented at the IEEE symposium on Logic in computer science
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Formal verification in a commercial setting
DAC '97 Proceedings of the 34th annual Design Automation Conference
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Modelling Asynchrony with a Synchronous Model
Proceedings of the 7th International Conference on Computer Aided Verification
An Efficient Partial Order Reduction Algorithm with an Alternative Proviso Implementation
Formal Methods in System Design
Handbook of automated reasoning
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We describe a method for verifying hardware whose correct behavior depends upon its software interface. It is presumed that the hardware is presented as a synchronous RTL model whereas the software is presented as an asynchronous abstraction. Our methodology incorporates partial order reduction on the software side, and localization reduction, to deal with the computational complexity of the verification. The partial order reduction is implemented as a constraint on the transition relation of a synchronous transformation of the software model. The reduced transformed model then may be verified using a verification algorithm whose scope is purely synchronous models, without modification. Thus, independent of the interface verification problem, this gives a general method for combining partial order reduction with symbolic model-checking.