8.4 Undetectable Fault Removal of Sequential Circuits Based on Unreachable States

Authors:
H. Yotsuyanagi;K. Kinoshita
Affiliations:
-;-
Venue:
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Year:
1998

Citing 7
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Abstract

We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable states and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.