CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Genetic algorithms + data structures = evolution programs (3rd ed.)
Genetic algorithms + data structures = evolution programs (3rd ed.)
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the high complexity of the problem of generating test patterns for digital circuits Genetic Algorithms (GA) have been investigated as an alternative to deterministic algorithms for test generation. In this paper a Genetic Algorithm "GATPG" is presented for generating sequences of test vectors for sequential circuits. The aim is to produce compact test sequences that attain high fault coverage. Because of the constraints imposed on a GA by the peculiar characteristics of sequential circuits it is proposed here a non-uniform selection probability for crossover combined with individuals (test sequences) of variable length and a two-phase fitness function. For the evaluation of candidate test sequences is used a 3-valued fault simulator, allowing the test patterns to be applied on faulty circuits that start from an arbitrary (unknown) state. Experimental results with respect to the ISCAS'89 benchmarks are presented to show the viability of the proposed approach.