A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
IEEE Transactions on Computers
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Journal of Electronic Testing: Theory and Applications
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to their simplicity transition faults are often used as targetsfor test generation to detect delay defects. However, one concerndocumented in the literature is that of over testing. One of thereasons for overtesting is that DFT approaches, such as scan,change sequentially untestable faults into testable faults. Oneapproach to reducing overtesting is to identify sequentiallyuntestable and redundant faults and not target them during testgeneration for the circuit with scan. Another application ofidentifying untestable transition faults is its use in logicoptimization. In this work efficient procedures to identifyuntestable and redundant transition faults in non-scansynchronoussequential circuits are investigated. Experimental results forISCAS-89 benchmark circuits are presented.