Maximizing Impossibilities for Untestable Fault Identification

Authors:
M. Hsiao
Affiliations:
The Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

This paper presents a new fault-independent method for maximizing local conflicting value assignments for the purpose of untestable faults indentification.The technique first computes a large number of logic implications across multiple time-frames and stores them in an implication graph.Then, by maximizingconflicting scenarios in the circuit, the algorithm identifies a large number of untestable faults that require such impossible combinations locally around each Boolean gate in the circuit, and its complexity is this linear in the number of nodes, resulting in short execution times.Experimental results for both combinational and sequential benchmark circuits showed that many more untestable faults can be identified with this approach efficiently.