PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams
Journal of Electronic Testing: Theory and Applications
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
On-line functionally untestable fault identification in embedded processor cores
Proceedings of the Conference on Design, Automation and Test in Europe
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The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different ...