On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 3rd conference on Computing frontiers
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs
Journal of Electronic Testing: Theory and Applications
Evolutionary functional recovery in virtual reconfigurable circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Fault tolerant techniques for reconfigurable platforms
Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India
SEU-aware resource binding for modular redundancy based designs on FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design
Journal of Electronic Testing: Theory and Applications
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The growing adoption of SRAM-based FieldProgrammable Gate Arrays (FPGAs) in safety-criticalapplications demands for efficient methodologies forevaluating their reliability. Single Event Upsets (SEUs)affecting the configuration memory of SRAM-basedFPGAs are a major concern, since they can permanentlyaffect the function implemented by the device. Weexploited a fault-injection environment developed at ourinstitution to analyze the impact of such faults on SRAM-basedFPGAs when fault tolerant design techniques areadopted. The experimental results allow quantitativeevaluations of the effects of these faults, and show that thesensitivity of the TMR design technique mainly dependson the characteristics of the adopted TMR architecture interms of placing and routing.