Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
Finite field for scientists and engineers
Finite field for scientists and engineers
Fault-tolerant decoders for cyclic error-correcting codes
IEEE Transactions on Computers
An Efficient Class of Unidirectional Error Detecting/Correcting Codes
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
On t-Error Correcting/All Unidirectional Error Detecting Codes
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Unidirectional Byte Error Detecting Codes for Computer Memory Systems
IEEE Transactions on Computers
Computer Organization
Design of self-checking digital networks using coding techniques
Design of self-checking digital networks using coding techniques
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Software pioneers: contributions to software engineering
Software pioneers: contributions to software engineering
A multiple bit upset tolerant SRAM memory
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
Proceedings of the 1st conference on Computing frontiers
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors
Journal of Electronic Testing: Theory and Applications
Design of parallel fault-secure encoders for systematic cyclic block transmission codes
Microelectronics Journal
Decoding shortened Reed Solomon codes at bit level
WSEAS TRANSACTIONS on COMMUNICATIONS
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A fault-detecting, bidirectional data interface between uncoded data from one component, such as a processor, and coded data in the rest of the system is described. This interface is capable of correcting a single multibit symbol error or detecting the occurrence of two such errors. The device uses a shortened Reed-Solomon code, and two practical symbol sizes are considered; nibble (4-bit) errors are protected by a (40, 32) binary equivalent shortened code, and byte errors are covered by a (80, 64) binary-sized code. The Reed-Solomon codes have maximum protection levels, even when shortened, and allow simplifying the design options. A dual orthogonal basis used for the symbols' representations provides significant hardware savings. The interface unit achieves internal fault detection by comparing regenerated parity values in a totally self-checking equality checker. A fault-tolerant ultrareliable memory module is proposed and evaluated. An illustrative design is realized using a single desktop programmable gate array.